The present disclosure relates generally to semiconductor devices and, more specifically, to a semiconductor device comprising a spacer having at least one batch layer and at least one non-batch layer.
The present disclosure is related to U.S. patent Ser. No. 10/614,388, which is assigned to the same assignee as the present invention, and which is hereby incorporated by reference.
The relentless demands for increased performance, decreased size and reduced manufacturing costs of semiconductor devices has increased the number of individual processes collectively performed during the fabrication of a “batch” or group of wafers. It is reported that a decrease in a characteristic dimension of a semiconductor device feature is accompanied by a proportional increase in the number of steps required to completely form the device. For example, the recent decrease of semiconductor device gate widths from 0.25 μm to 0.13 μm required a substantially proportional increase in fabrication steps from about 240 steps to about 360 steps. Therefore, individual cycle time becomes a critical consideration in the operation of a device fabrication foundry. For example, thermal processing may account for about 45% of the total time required to produce a single lot of semiconductor devices.
Consequently, semiconductor fabrication technology has experienced a trend away from batch processing and toward single wafer processing. Single wafer processes have significantly shorter thermal cycle times because they may employ rapid thermal processes (RTP), such as those employing infra-red lamps to quickly heat up a wafer to a process temperature. By replacing batch furnace processes with single wafer processes, product fabrication cycle times can be dramatically reduced. Moreover, single wafer processes allow for greater flexibility in handling complicated product combinations, thereby enabling fabrication facilities to better cater to a customer's needs. Another advantage of single wafer processing is that a much lower loss in product can occur with single wafer processing compared to batch processing, because a large plurality of wafers can be lost in the event of a catastrophic failure during batch processing, whereas only a few or a single wafers can be lost in the event of a catastrophic failure during single wafer processing. Single wafer processing also allows timely investigation for quality, reliability, research and development.
However, problems can arise when replacing batch processes with single wafer processes. For example, employing single wafer processing during the fabrication of spacers conventionally formed on opposing sides of a semiconductor device gate stack can result in excessive current between the gate stack and the device well. Single wafer processing of the spacers can also be deleterious to hot carrier injection performance as compared to batch processing.
Accordingly, what is needed in the art is a semiconductor device and method of manufacturing thereof that addresses the above-discussed issues.